The present invention relates to data acquisition technology for a data processing system, and more specifically to technology that is most suitably applied to an emulator, a system evaluation apparatus using the same, a method of configuring trace memories used to acquire signals on a bus in an emulator and to a trace control method.
An emulator is used to make a detailed evaluation of a newly developed microcomputer-based system or microprocessor-based system (hereinafter referred to as a user system).
System evaluation apparatuses include, for example, an evaluation microcomputer or microprocessor that substitutively perform functions of a microcomputer or microprocessor used in the user system, and an in-circuit emulator having a trace memory for acquiring signals on a user system bus in a target user system, both being connected between a host computer such as a personal computer and the target user system. By executing a user program and an emulation program alternately, the system evaluation apparatuses analyze data that are stored in a trace memory while the user program is being executed, thus performing debugging.
In the emulator, there is a problem that if an address access time of the trace memory used to take in signals on the user system bus is relatively long compared with the operation frequency of the microcomputer or microprocessor to be used in the user system, the trace data may be lost. Japanese Patent Laid-Open No. 52013/1994 has proposed an emulator in which the trace memory is made up of a plurality of banks, and the data are stored alternately so as to prevent loss of trace data.
Because the memory capacity of the trace memory is finite and because the amount of data to be taken in per unit time has been increasing with the increasing operation frequency of the microcomputer or microprocessor, taking all the signals on the bus into the trace memory during the execution of the user program is not an appropriate technique to be used by an emulator. Thus it was proposed to set certain conditions (trace conditions) and store the signals on the bus in the trace memory only when the signals meet the trace conditions to reduce the amount of the data to be traced.
To meet these requirement, a trace system was proposed in which the trace memory is formed into two memory banks and data are stored alternately in each memory bank. Appropriate trace conditions are set up, and signals or data meeting the trace conditions are stored. However, there arises a problem that valid trace data such as the data meeting the trace conditions are not always stored alternately in the two memory banks of the trace memory. That is, the valid trace data are stored unevenly in one of the banks. Thus the order in which the trace data are stored in the two memory banks as the trace memory cannot be easily determined. Therefore, an appropriate debugging cannot be performed.